Cirrus Logic CS8130 - Manual (Page 26)

Digital Pins
RXD - Receiver Data Output
Receiver output data. Normally connected to RxD on the UART.
TXD - Transmit Data Input
Transmitter input data. Normally connected to TxD on the UART.
D/C - Data/Control Mode Input
The D/C pin determines whether the input data on TXD is treated as data to be transmitted via
the LED, or as control information to set up the CS8130 internal registers. The D/C pin also
can act as a power down control.
FORM/BSY - Received Data Format Output/Busy Signal Output
If auto format detect mode is enabled, this pin indicates the format of the incoming data.
FORM is low for ASK format data, and high for IRDA/HPSIR format data.
In TV remote data mode (Mode 3), this pin becomes a handshake signal to the UART.
FORM/BSY low means OK to send a character. FORM/BSY high means "I am busy, do not
send another character".
PWRDN - Power Down Control Input
PWRDN low places the CS8130 into a very low power consumption "off" state.
RESET - Reset Input
RESET low places all the internal logic into a known state. All the control register bits are
forced high or low, as defined in the register definition section. If the crystal oscillator is in use,
then RESET must be held low for >25 ms, with PWRDN high and power applied. If an
external clock is used, then the RESET pulse can be short (>1
µ
s).
XTALIN, XTALOUT - Crystal Connections
To use the internal oscillator, connect either a 3.6864 MHz or a 1.8432 MHz crystal between
XTALOUT and XTALIN. If using an external clock, connect XTALIN to DGND.
EXTCLK - External Clock Input or Output
If no crystal is present on XTALIN and XTALOUT, EXTCLK becomes an input. A
3.6864 MHz or 1.8432 MHz clock should be connected to EXTCLK. XTALIN should be
connected to DGND.
If a crystal is present on XTALIN and XTALOUT, EXTCLK becomes an output. EXTCLK will
output the same frequency as the crystal. The EXTCLK output driver may be disabled to
conserve power.
CLKFR - Clock Frequency Select Input
Tie CLKFR to ground to select a 3.6864 MHz clock. Connect CLKFR to the VD+ pin to select
a 1.8432 MHz clock.
CS8130
26 DS134PP2
CS8130
26 DS134F1