Cirrus Logic CS8130 - Manual (Page 21)

Register 28, CS8130 Silicon Revision Register
D3 D2 D1 D0
REV3 REV2 REV1 REV0
Register
BIT NAME VALUE FUNCTION
REV3-0 CS8130 silicon
revision level 0000 1st silicon, designed to meet DS134PP2 data sheet,
dated June 1994
This register should be read by the CS8130 driver to allow CS8130 future enhancements to be recog-
nized, and incorporated into future versions of the driver.
Register 24, Receive ASK Timing Sensitivity Register
D3 D2 D1 D0
RAT3 RAT2 RAT1 RAT0
0 0 0 0
Register
Reset (R)
BIT NAME VALUE FUNCTION
RAT3-0 Receiver ASK
Timing Sensitivity.
Timing window =
+0.27
µ
s to
-RAT(2/3.6864E06)
- 0.27
µ
s
0000
0001
0010
↓
1111
0 R
1
2
↓
15
+0.27
µ
s to -0.27
µ
s window (500 kHz ASK mode)
+0.27
µ
s to -0.54 - 0.27
µ
s window
+0.27
µ
s to -1.08 - 0.27
µ
s window
↓
+0.27
µ
s to -8.14 - 0.27
µ
s window
The timing window is relative to the modulation divider register nominal setting.
CS8130
DS134PP2 21
CS8130
DS134F1 21