Cirrus Logic CS5513 - Manual (Page 7)

CS5510/11/12/13
DS337F4 7
SWITCHING CHARACTERISTICS - CS5510/12
(T
A
= 25° C; V+ = 5 V ±5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; C
L
= 50 pF)
Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or
200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded
linearity specifications, as shown in Figures 14 and 15.
21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
22. On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as
well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for t
SLP
or longer,
the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for t
WAKE
or
longer.
Parameter Symbol Min Typ Max Unit
Master Clock Timing
Master Clock Frequency (CS5510) (Note 20) SCLK 10 32.768 130 kHz
Master Clock Frequency (CS5512) (Note 20) SCLK 10 32.768 200 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times (Note 21)
CSB
SCLK
SDO
t
rise
-
-
- -
-
50
1.0
10
-
µs
µs
ns
Fall Times (Note 21)
CSB
SCLK
SDO
t
fall
-
-
- -
-
50
1.0
10
-
µs
µs
ns
Serial Port Timing
Serial Clock Frequency (CS5510) (Note 22) SCLK 10 32.768 130 kHz
Serial Clock Frequency (CS5512) (Note 22) SCLK 10 32.768 200 kHz
SCLK High to Enter Sleep (Note 22) t
SLP
200 - 2000 µs
SCLK Low to Exit Sleep (Note 22) t
WAKE
10 - - µs
Serial Clock Pulse Width High
Pulse Width Low
t
1
t
2
2
2 -
- 60
60 µs
µs
SDO Read Timing
CS to Data Valid t
3
- - 150 ns
SCLK Falling to New Data Bit t
4
- - 150 ns
CS Rising to SDO Hi-Z t
5
- - 150 ns
CS Falling to SCLK Rising t
11
200 - - ns