Cirrus Logic CS5463 - Manual (Page 10)

CS5463
10 DS678F3
Notes: 10. All measurements performed under static conditions.
11. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external
oscillator is used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between
2.5 MHz - 5.0 MHz.
12. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this
specification.
13. The frequency of CPUCLK is equal to MCLK.
14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is
limited by the full-scale signal applied to the channel input.
15. Configuration Register bits PC[6:0] are set to “0000000”.
16. The MODE pin is pulled low by an internal resistor.
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IL
-
-
- -
-
- 0.48
0.3
0.2
VD+
V
V
V
High-level Output Voltage I
out
= +5 mA V
OH
(VD+) - 1.0 - - V
Low-level Output Voltage I
out
= -5 mA V
OL
- - 0.4 V
Input Leakage Current (Note 16) I
in
- ±1 ±10 µA
3-state Leakage Current I
OZ
- - ±10 µA
Digital Output Pin Capacitance C
out
- 5 - pF
Parameter Symbol Min Typ Max Unit