beautypg.com

Figure 16. left-justified format, 7 initialization, 8 recommended power-up sequence – Cirrus Logic CS53L21 User Manual

Page 32: 7 initialization 4.8 recommended power-up sequence, Figure 16.left-justified format, Recommended power, Illus, Cs53l21

background image

32

DS700PP1

CS53L21

4.7

Initialization

The initialization and Power-Down sequence flowchart is shown in

Figure 17 on page 33

. The A/D enters a

Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators
and control port registers are reset. The internal voltage reference, ADC and switched-capacitor low-pass
filters are powered down.

The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-
cessible once RESET is high and the desired register settings can be loaded per the interface descriptions
in

“Software Mode” on page 34

. If a valid write sequence to the control port is not made within approximately

10 ms, the A/D will enter Hardware Mode.

Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+ will begin powering
up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then ap-
plied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted
state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio and normal operation begins.

4.8

Recommended Power-Up Sequence

1. Hold RESET low until the power supplies are stable.
2. Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode.
3. For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-

by”.

4. Load the desired register settings while keeping the PDN bit set to ‘1’b.
5. Start MCLK to the appropriate frequency, as discussed in

Section 4.5

.

6. Set the PDN bit to ‘0’b.
7. Apply LRCK and SCLK for normal operation to begin.
8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to

prevent power glitch related issues.

LRCK

SCLK

M S B

L S B

M S B

L S B

L eft C h a n n el

Rig ht C h a n n el

SDIN

MSB

AOUTA / AINxA

AOUTB / AINxB

Figure 16. Left-Justified Format