Cirrus Logic CS53L21 - Manual (Page 15)

DS700PP1 15
CS53L21
7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are
settled.
8. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies.
9. See “Master” on page 30 .
10. “MCLK” refers to the external master clock applied.
Master Mode (Note 9)
Output Sample Rate (LRCK) All Speed Modes
(Note 10)
F
s
- Hz
LRCK Duty Cycle 45 55 %
SCLK Frequency 1/t
P
- 64•F
s
Hz
SCLK Duty Cycle 45 55 %
LRCK Edge to SDOUT MSB Output Delay t
d(MSB)
- 52 ns
SDOUT Setup Time Before SCLK Rising Edge t
s(SDO-SK)
20 - ns
SDOUT Hold Time After SCLK Rising Edge t
h(SK-SDO)
30 - ns
Parameters Symbol Min Max Units
MCLK
128
-----------------
t
h(SK-SDO)
//
//
//
//
//
//
MSB MSB-1
LRCK
SCLK
SDOUT
t
d(MSB)
t
s(LK-SK)
t
P
t
s(SDO-SK)
Figure 3. Serial Audio Interface Slave Mode Timing
t
h(SK-SDO)
//
//
//
//
//
//
MSB MSB-1
LRCK
SCLK
SDOUT
t
d(MSB)
t
P
t
s(SDO-SK)
Figure 4. Serial Audio Interface Master Mode Timing