Cirrus Logic CS4953xx - Manual (Page 35)

CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705F2 35
10 Revision History
Revision Date Changes
A1 February, 2006 Advance release.
A2 June, 2006 Updated part numbers for ordering (Tables 5 & 6), Updated V
OH
and V
OL
specification to include the current load used for testing
A3 July, 2006 Updated part numbers for ordering (Tables 5 & 6). Updated text in sections 3 and 4.
Updated parameter descriptions in sections 5.1 and 5.3. Updated Tspickl, Tspickh,
and Tspidov timing. Corrected Figure SPI Master Timing to use EE_CS. Added foot-
note to XTI table. Removed SCLK/LRCLK relative timing from DAI port timing.
Removed SCLK/LRCLK slave relative timing from DAO port timing.
A4 October, 2007 Updated the Tspidsu, Tspickl, and Tspickh timing parameters for master mode SPI.
This applies to both SPI ports.
PP1 May, 2008 Updated product feature list in Table 2 . Updated Figure 19 and Figure 21 .
PP2 June, 2008 Added typical crystal frequency values in Table Footnote 1 and minimum and
maximum values of F
xtal
in Section 5.8 . Redefined Master mode clock speed for
SCP_CLK in Section 5.11 . Redefined DC leakage characterization data in
Section 5.3 , correcting units of measurement. Modified Footnote 1 under
Section 5.10 .
PP3 September, 2008 Removed references to External Parallel Flash / SRAM Interface.
PP4 June, 2009 Updated product number references in Section 5.9 , Section 6 , Section 7 , Table
2 , . Table 3 , and Table 4 . For all Active Low pins, changed Active Low pin
designation from “#” character after the pin name to a line over the pin name as in
“EE_CS”. Removed Active Low designation from the BDI_REQ pin in the 128-pin
pinout drawings in
Figure 19 and Figure 20 , and in the 144-pin pinout drawings in
Figure 21 and Figure 22 . Updated the pin names referred to in the timing diagrams
in Figure 9 , Figure 10 , Figure 17 , and Figure 18 . Updated the parameters in Section
5.15 .
PP5 July, 2009 Updated Figure 19 , Figure 20 , Figure 21 . Removed CS495314-CQZ and
CS495314-CQZR from Table 5 and Table 6 . Added recommendation that CS4953x4
family be used with new designs. Updated Section 2
PP6 November, 2009 Removed references to UART port. Removed references to 11.2896,
18.432, and 27 MHz frequency clocks in Note 1 in
Section 5.8 “Switching
Characteristics — XTI” on page 12 and the minimum and maximum
External Crystal Operating Frequency values in that same section. Updated
Section 5.17 “Switching Characteristics — Digital Audio Output Port” on
page 24
. In Figure 21, "144-pin LQFP Pin-Out Drawing (CS495313)", on
page 32 , moved SCP2_SDA from Pin 106 to Pin 105, deleted duplicate
EE_CS from Pin 25, and designated Pin 140 BDI_REQ as active low.
Designated Pin 32, BDI_REQ as active low In
Figure 19, "128-pin LQFP
Pin-Out Drawing (CS495303/CS495313)", on page 30 and in Figure 20,
"128-pin LQFP Pin-Out Drawing (CS495304/CS495314)", on page 31 . In
Section 5.3 , the parameter, “Input leakage current (all digital pins with
internal pull-up resistors enabled, and XTI)”, Max value changes from 50 μA
to 70
μA. In
Section 5.13 , the parameter SCP_CLK low to SCP_SDA out
valid with symbol “tiicdov” maximum value changes from 18 ns to 36 ns.
PP7 June, 2010 Updated Table 5 to show status of various parts.