Cirrus Logic CS4953xx - Manual (Page 24)

CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705F2 24
5.17 Switching Characteristics — Digital Audio Output Port
Figure 13. Digital Audio Port Output Timing Master Mode
Parameter Symbol Min Max Unit
DAO_MCLK period T
daomclk
40 — ns
DAO_MCLK duty cycle — 45 55 %
DAO_SCLK period for Master or Slave mode
1
1. Master mode timing specifications are characterized, not production tested.
T
daosclk
40 — ns
DAO_SCLK duty cycle for Master or Slave mode
1
— 40 60 %
Master Mode (Output A1 Mode)
1,2
2. Master mode is defined as the CS4953xx driving both DAO_SCLK and DAO_LRCLK. When MCLK is an input, it is
divided to produce DAO_SCLK, DAO_LRCLK.
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input t
daomsck
— 19 ns
DAO_SCLK delay from DAO_LRCLK transition
3
t
daomlrts
— 8 ns
DAO_LRCLK delay from DAO_SCLK transition
3
3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the
point at which the data is valid.
t
daomstlr
— 8 ns
DAO1_DATA[3:0], DAO2_DATA[1:0]
delay from DAO_SCLK transition
3
t
daomdv
— 10 ns
Slave Mode (Output A0 Mode)
4
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
DAO_SCLK active edge to DAO_LRCLK transition t
daosstlr
10 — ns
DAO_LRCLK transition to DAO_SCLK active edge t
daoslrts
10 — ns
DAO_Dx delay from DAO_SCLK inactive edge t
daosdv
— 12.5 ns
DAO_MCLK
DAO_SCLK
DAO_LRCLK
DAOn_DATAn
t
daomlclk
t
daomsck
t
daomdv
t
daomlrts
DAO_MCLK
DAO_SCLK
DAO_LRCLK
DAOn_DATAn
t
daomclk
t
daomsck
t
daomstlr
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK