3 sclk equals mclk, 4 mclk divide by 2, 5 mclk disable – Cirrus Logic CS42L55 User Manual
Page 44: 5 clocking control 2 (address 05h), 1 speed mode, P 44, Cs42l55
44
DS773F1
CS42L55
6.4.3
SCLK Equals MCLK
Configures the SCLK signal source and speed for master mode.
6.4.4
MCLK Divide By 2
Configures a divide of the input MCLK prior to all internal circuitry.
6.4.5
MCLK Disable
Configures the MCLK signal prior to all internal circuitry.
Note:
This function should be enabled during power down (PDN=1) ONLY.
6.5
Clocking Control 2 (Address 05h)
6.5.1
Speed Mode
Configures the speed mode of the CODEC in slave mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in master mode.
Notes:
1.
Slave/Master Mode is determined by the M/S bit in
“Master/Slave Mode” on page 43
2.
Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(
“32 kHz Sample Rate Group” on page 45
) and the RATIO[1:0] bits (
). Low sample rates may also affect dynamic range performance in the typical audio band.
Refer to the referenced application for more information.
SCK=MCK[1:0]
Output SCLK
00
Re-timed, bursted signal with minimal speed needed to clock the required data samples
01
Reserved
10
MCLK signal after the MCLK divide (MCLKDIV2) circuit
11
MCLK signal before the MCLK divide (MCLKDIV2) circuit
MCLKDIV2
MCLK signal into CODEC
0
No divide
1
Divided by 2
Application:
“Serial Port Clocking” on page 34
MCLKDIS
MCLK signal into CODEC
0
On
1
Off; Disables the clock tree to save power when the CODEC is powered down.
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
SPEED1
SPEED0
32kGROUP
RATIO1
RATIO0
SPEED[1:0]
Serial Port Speed
00
Reserved
01
Single-Speed Mode (SSM)
10
Half-Speed Mode (HSM)
11
Quarter-Speed Mode (QSM)
Application:
“Serial Port Clocking” on page 34