Cirrus Logic CDB42438 - Manual (Page 5)

CDB42438
DS646DB2 5
clock on the OMCK input pin, and can operate in either the Left-Justified or I²S interface for-
mat.
Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of
the Cirrus Logic FlexGUI software. Refer to register “CS8406 Control (address 04h)” on
page 17 for configuration settings.
1.6 CS8416 Digital Audio Receiver
A complete description of the CS8416 receiver (Figure 10 on page 32) and a discussion of
the digital audio interface are included in the CS8416 data sheet.
The CS8416 converts the input S/PDIF data stream into PCM data for the CS42438 and op-
erates in master or slave mode, generating either a 128Fs or 256Fs master clock on the
RMCK output pin, and can operate in either the Left-Justified or I²S interface format.
Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of
the Cirrus Logic FlexGUI software. Refer to register “CS8416 Control (address 05h)” on
page 18 for configuration settings.
1.7 CS5341
A complete description of the CS5341 Audio ADC (Figure 20 on page 42) is included in the
CS5341 data sheet.
The CS5341 is connected to the AUX port of the CS42438 and is used only in the TDM in-
terface format of the CODEC. The AUX port of the CS42438 masters the CS5341 and ac-
cepts either Left-Justified or I²S data on AUX_SDIN.
Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of
the Cirrus Logic FlexGUI software. Refer to register “CS5341 and Miscellaneous Control (Ad-
dress 08h)” on page 22 for configuration settings.
1.8 Canned Oscillator
Oscillator Y1 provides a system master clock. This clock is routed through the CS8416 and
out the RMCK pin when the S/PDIF input is disconnected (refer to the CS8416 data sheet for
details on OMCK operation). To use the canned oscillator as the source of the MCLK signal,
remove the S/PDIF input to the CS8416 and configure the CS8416 appropriately.
The oscillator is mounted in pin sockets, allowing easy removal or replacement.The board is
shipped with a 12.2880 MHz crystal oscillator populated at Y1.
1.9 External Control Headers
The evaluation board has been designed to allow interfacing with external systems via the
headers J11 and J24.
The 10-pin, 2 row header, J24, provides access to the serial audio signals required to inter-
face with a DSP (see Figure 9 on page 31).