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3 codec clock control (address 03h), Table 2. clocks tocodec, 4 cs8406 control (address 04h) – Cirrus Logic CDB42438 User Manual

Page 17: Table 3. data to cs8406, Table 2. clocks tocodec table 3. data to cs8406, P 17

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CDB42438

DS646DB2

17

5.3

CODEC CLOCK CONTROL (ADDRESS 03H)

5.3.1

MUX (CLK_MUX)

Default = 11

Function:

This MUX selects the sub-clock lines from the DSP Header and the sub-clocks from the TDMer in-
ternal to the FPGA (see Figure 3 on page 10).

5.3.2

FPGA CLOCKS TO CODEC CLOCKS (FPGA->CODEC)

Default = 0
0 - FPGA Masters CODEC clock bus
1 - FPGA Slave to CODEC clock bus

Function:

This bit toggles a control line for the internal clock buffer to the CODEC serial port (see Figure 3 on
page 10)
.

5.4

CS8406 CONTROL (ADDRESS 04H)

5.4.1

DATA MUX(MUX)

Default = 100

7

6

5

4

3

2

1

0

Reserved

Reserved

Reserved

Reserved

Reserved

CLK_MUX1

CLK_MUX0

FPGA->CODEC

CLK_MUX[1:0]

Clock Selection

00

Reserved

01

Reserved

10

DSP

11

TDMer

Table 2. Clocks toCODEC

7

6

5

4

3

2

1

0

Reserved

Reserved

MUX2

MUX1

MUX0

128/256 Fs

I²S/LJ

Reserved

MUX[2:0]

Data Selection

000

Reserved

001

Reserved

010

Reserved

011

Reserved

100

ADC1 (from ADC_SDOUT)

101

ADC2 (from ADC_SDOUT)

110

ADC3 (from ADC_SDOUT)

111

EXT_ADC (from ADC_SDOUT)

Table 3. Data to CS8406