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Internal sub-clock routing, Figure 3. internal sub-clock routing, Sections 3.2 to 3.4 show graphical descriptions – Cirrus Logic CDB42438 User Manual

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CDB42438

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DS646DB2

3.2.

Internal Sub-Clock Routing

The graphical description below shows the internal clock routing topology between the CS42438,
CS8416, CS8406 and DSP Header. Refer to registers “CODEC Clock Control (address 03h)” on
page 17, “CS8406 Control (address 04h)” on page 17 and “CS8416 Control (address 05h)” on
page 18 for configuration settings.

CS8416

DSP Header

LRCK

CS8406

CS42438

FS

SCLK

AUX_LRCK

AUX_SCLK

SCLK

DSP FS

DSP SCLK

LRCK

SCLK

DSP_FS

FS

CODEC_CLK.MUX[1:0]

AUX LRCK

AUX SCLK

CS8416 LRCK

CS8416 SCLK

DSP_FS

DSP_SCLK

AUX LRCK

AUX SCLK

TDMer

M/S

FPGA->CODEC

FS

256Fs

256Fs

CODEC_CLK.MUX[1:0]

FPGA->CODEC

DSP_SCLK

Figure 3. Internal Sub-Clock Routing

See also other documents in the category Cirrus Logic Hardware: