Cirrus Logic CS42428 - Manual (Page 63)

DS605F2 63
CS42428
9.1.3 Circuit Board Layout
Board layout and capacitor choice affect each other and determine the performance of the PLL. Figure
26 illustrates a suggested layout for the PLL filter components and for bypassing the analog supply volt-
age. The 10 µF bypass capacitor is an electrolytic in a surface-mount case A or thru-hole package. RFILT,
CFILT, CRIP, and the 0.1 µF decoupling capacitor are in an 0805 form factor. The 0.01 µF decoupling
capacitor is in the 0603 form factor. The traces are on the top surface of the board with the IC so that there
is no via inductance. The traces themselves are short to minimize the inductance in the filter path. The
VA and AGND traces extend back to their origin and are shown only in truncated form in the drawing.
VA AG
ND
LP
FL
T
CFILT
RFI
L
T
CRIP
0.1 µF
0.01 µF
10 µF
= via to ground plane
Figure 26. Recommended Layout Example