Cirrus Logic CS42428 - Manual (Page 29)

DS605F2 29
CS42428
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
LSB M SB
20 clks
64 clks 64 clks
LS B MSB LS B M SB LSB M SB LSB M SB LSB MSB MSB
DAC1 DAC3 DAC5 DAC2 DAC4 DAC6
20 clks 20 clks 20 clks 20 clks 20 clks
Left Channel Right C hannel
20 clks
DAC7 DAC8
20 clks
DAC_SDIN4
20 clks
A DC1 A DC3 A DC5 A DC2 A DC4 A DC6
20 clks 20 clks 20 clks 20 clks 20 clks
ADC_SDOUT
DAC_SDIN1
Figure 14. One Line Mode #1 Serial Audio Format
One Line Data Mode #1, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
20 128 Fs 128 Fs single-speed mode
128 Fs 128Fs double-speed mode
LSB M SB
24 clks
128 clks
LS B MSB LS B M SB LSB M SB LSB M SB LSB MSB MSB
DAC1 DAC3 DAC5 DAC2 DAC4 DAC6
24 clks 24 clks 24 clks 24 clks 24 clks
Left Channel Right Channel
24 clks
DAC7 DAC8
24 clks
24 clks
A DC1 A DC3 A DC5 A DC2 A DC4 A DC6
24 clks 24 clks 24 clks 24 clks 24 clks
128 clks
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
ADC_SDOUT
DAC_SDIN1
DAC_SDIN4
Figure 15. One Line Mode #2 Serial Audio Format
One Line Data Mode #2, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
24 256 Fs not supported single-speed mode