Cirrus Logic CS42426 - Manual (Page 38)

38 DS604F2
CS42426
4.8 Reset and Power-Up
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be activated if the analog or digital supplies
drop below the recommended operating condition to prevent power-glitch-related issues.
When RST is low, the CS42426 enters a low-power mode and all internal states are reset, including the
control port and registers, and the outputs are muted. When RST is high, the control port becomes opera-
tional, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the
Power Control Register will then cause the part to leave the low-power state and begin operation. If the in-
ternal PLL is selected as the clock source, the serial audio outputs will be enabled after the PLL has settled
(see
“Power Control (address 02h)” on page 43 for more details).
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time
delay of approximately 80 ms is required after applying power to the device or after exiting a reset state.
During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.
4.9 Power Supply, Grounding, and PCB Layout
As with any high-resolution converter, the CS42426 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure
5 and 6 show the recommended power
arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from
the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this
case, no additional devices should be powered from VD.
For applications where the output of the PLL is required to be low jitter, use a separate, low-noise analog
+5 V supply for VA, decoupled to AGND. In addition, a separate region of analog ground plane around the
FILT+, VQ, LPFLT, REFGND, AGND, and VA pins is recommended.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42426 as pos-
sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same
side of the board as the CS42426 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and
PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the
electrical path from FILT+ and REFGND. The CDB42428 evaluation board demonstrates the optimum lay-
out and power supply arrangements.