Cirrus Logic CS42426 - Manual (Page 37)

DS604F2 37
CS42426
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in
Figure 23 , the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
4.7 Interrupts
The CS42426 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may be set to be active low, active high or active low with
no active pull-up transistor. This last mode is used for active low, wired-OR hook-ups, with multiple periph-
erals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see “Interrupt
Status (address 20h) (Read Only)” on page 56 ). Each source may be masked off through mask register bits.
In addition, each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option
of level-sensitive or edge-sensitive modes within the microcontroller, many different configurations are pos-
sible, depending on the needs of the equipment designer.
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START
ACK
STOP
ACK
ACK ACK
1 0 0 1 1 AD1 AD0 0 SDA 1 0 0 1 1 AD1 AD0 1
CHIP ADDRESS (READ)
START
INCR 6 5 4 3 2 1 0 7 0 7 0 7 0
NO
16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 23. Control Port Timing, I²C Read