An379 – Cirrus Logic AN379 User Manual
Page 9
AN379
AN379REV2
9
The CS1680 maximum switching frequency is 312.5kHz. Test results indicate that optimal performance is
obtained in the range of 75kHz to 225kHz. Higher frequencies allow the use of smaller magnetics, but
switching losses increase. Selecting too low a full brightness switching frequency risks allowing the minimum
frequency to drop into the audible range. Equation 1 defines the buck stage switching frequency TT
BUCK(fb)
at
full brightness:
Using the full brightness frequency, determine the value of critical period (T1
BUCK
+T2
BUCK
) using Equation 2:
where
T3
BUCK
= the idle time added at the end of time (T1
BUCK
+T2
BUCK
)
The resonant frequency is defined by the magnetizing inductance and the parasitic capacitance at the drain of
power FET Q
BUCK
, which includes the parasitic capacitance across the buck inductor winding, power FET
Q
BUCK
drain to source, and the reflected capacitance due to catch diode D
BUCK
. The buck inductance
resonates with the total parasitic capacitance of the drain node and is calculated using Equation 3:
where
L
BUCK
= buck inductance
C
P
= total parasitic capacitance at the drain of power FET Q
BUCK
During full brightness circuit operation, the circuit is delivering full nominal power to the LED string. When
power FET Q
BUCK
turns on, current flows through the LED string, inductor L
BUCK
winding, FET Q
BUCK
, and
resistor R
BUCK(Sense)
. The current rises linearly from zero to a preset maximum peak current I
BUCKPK
defined
by sense resistor R
BUCK(Sense)
and the internal IC threshold. The gate is driven high for as long as is required
to reach peak current I
BUCKPK
. The controller has a maximum turn-on time T1
BUCK
limit set to 6.5
s, after
which the gate is turned off.
During period T2
BUCK
, the buck inductor current decays linearly, transferring the energy stored in the inductor
to the load. At the end of period T2
BUCK
, the current in the inductor is zero. However, some energy is stored
in parasitic capacitance C
P
charged to voltage V
OUT
. Capacitance C
P
and inductance L
BUCK
oscillate until the
losses exhaust the energy stored in capacitor C
P
.
The zero-current detection circuit looks for the first zero-crossing of the oscillation after period T2
BUCK
, and
starts a timer that determines the duration of idle time T3
BUCK
. Once the idle time is depleted the control loop
turns on power FET Q
BUCK
to start a new cycle. Extending idle time T3
BUCK
, when no current flows in the load
circuit, dilutes the energy delivered during time T1
BUCK
and T2
BUCK
resulting in lower average power to the
load.
TT
BUCK fb
1
F
BUCKSW
--------------------------
=
[Eq. 1]
T1
BUCK
T2
BUCK
+
1
F
BUCKSW
-------------------------- T3
BUCK
–
TT
BUCK
T3
BUCK
–
=
=
[Eq. 2]
T3
BUCK
L
BUCK
C
P
=
[Eq. 3]