Ampro Corporation COM 830 - Manual (Page 32)

Chapter 3 Signals and Pinout Tables
26 Reference Manual COM 830
A-B Connector Signal Descriptions
Table 3-2. AC'97/Intel ® High Definition Audio Link Signals Descriptions
Signal Description
I/O PU/PD Comment
AC_RST# AC ’97/Intel High Definition Audio Reset: This
signal is the master hardware reset to external codec(s). O 3.3V
AC_SYN
C AC ’97/Intel High Definition Audio Sync: This signal
is a 48 kHz fixed rate sample sync to the codec(s). It is
also used to encode the stream number. O 3.3V AC_SYN
C is a boot
strap
signal (see
note
below)
AC_BIT_
CLK AC ’97 Bit Clock Input: This signal is a 12.288 MHz
serial data clock generated by the external codec(s).
This signal has an Intel integrated pull-down resistor.
Intel High Definition Audio Bit Clock Output: This
signal is a 24.000MHz serial data clock generated by
the Intel High Definition Audio controller (the Intel
ICH7M-DH). This signal has an Intel integrated pull-
down resistor so that AC_BIT_CLK doesn’t float when
an Intel High Definition Audio codec (or no codec) is
connected but the signals are temporarily configured as
AC ’97.
I 3.3V
O 3.3V
AC_SDO
UT AC ’97/Intel High Definition Audio Serial Data Out:
This signal is the serial TDM data output to the
codec(s). This serial output is double-pumped for a bit
rate of 48 Mb/s for Intel High Definition Audio. O 3.3V AC_SDO
UT is a
boot strap
signal (see
note
below)
AC_SDIN
[2:0] AC ’97//Intel High Definition Audio Serial Data In
[0]: These signals are serial TDM data inputs from the
three codecs. The serial input is single-pumped for a bit
rate of 24 Mb/s for Intel High Definition Audio. I 3.3V
NOTE Some signals have special functionality during the reset process. They may bootstrap
some basic important functions of the module.