ARM Cortex R4F - Manual (Page 402)

AC Characteristics
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-2
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15.1 Processor timing
The AXI bus interface of the processor conforms to the AMBA AXI Specification. For the
relevant timing of the AXI write and read transfers, and the error response, see the AMBA AXI
Protocol v1.0 Specification.
The APB debug interface of the processor conforms to the AMBA 3 APB Protocol v1.0
Specification. For the relevant timing of the APB write and read transfers, and the error
response, see the AMBA 3 APB Protocol v1.0 Specification.