13 c0, current cache level id register, Table 4-21, Current cache level id register bit functions -34 – ARM Cortex R4F User Manual

Page 118: Figure 4-25, Current cache level id register format -34

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13 c0, current cache level id register, Table 4-21, Current cache level id register bit functions -34 | Figure 4-25, Current cache level id register format -34 | ARM Cortex R4F User Manual | Page 118 / 456

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