Teledyne LeCroy QPHY-ENET - Manual (Page 64)

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QPHY-ENET Operator’s Manual Rev G
1. Set the Device Under Test for normal operation in Slave mode.
2. Use an active or differential probe (Minimum Bandwidth 1.5GHz) to probe the TX_TCLK on the Device
Under Test (slave).
3. Connect a second active or differential probe (Minimum Bandwidth 1.5GHz) to the TX_TCLK on the Link
Partner (master).
4. On the oscilloscope’s Ethernet Menu, enter which channels are connected to which signals.
5. Ensure that the DUT is receiving valid data by verifying the DUT GMII management register bit 10.13 is
set to 1.
6. Select 1000Base-T in the Select Standard field.
7. Select Slave TX_TCLK Jitter in the Select Test field.
8. Click the Set Up and Start Test button to begin the test. Acquire between 100ms and 1s of data (in
multiple acquisitions).
9. The parameter P1 shows the p-p jitter of the slave TX_TCLK relative to the master TX_TCLK. P2 is the
jitter in P1 filtered through a 32 kHz high-pass filter. P3 is a constant, it is the “worst Slave Jtxout”
measured during Step 1 (previous) that was entered on the “Jtxout values” tab of the oscilloscope’s
Ethernet Tests menu. P4 is the sum of P2 and P3. P5 is the simultaneously measured peak-to-peak
value of the MASTER jitter filtered by a 5kHz high-pass filter. P6 is P4-P5.
P1 must be less than 1.4 ns and the parameter P6 must be less than 400ps (which means, P4 must be no
more than 400ps greater than the simultaneously measured peak to peak Master jitter filtered by a 5KHz high
pass filter).
Note: The TX_TCLK signal is normally probed on one of the pins of the Ethernet PHY chip. Contact the PHY chip vendor to determine the
appropriate pin to probe. In many cases, this clock is not externally available.