Teledyne LeCroy QPHY-ENET - Manual (Page 55)

QPHY-ENET Software Option
QPHY-ENET Operator’s Manual Rev G
55
2. Use Differential Return Loss section of the board (G: recommended), for SMA cable connection (differential
probe can be used for section F).
3. Alternately, use the 1000BT template section as follows. Install jumpers on J77/J71 (the oscilloscope
connects to the DUT input signal) and install jumpers according to
X
Table 7
X
:
Pair Install Remove
A J39, J40 J61, J60, J62
B J43, J44 J59, J60, J62
C J41, J42 J59, J61, J62
D J45, J46 J59, J61, J60
Table 7. Mode 1 and 4 test Without Disturbing Signal
WARNING: Since J99 and J100 are not installed the input signal pair is not connected to the splitters. J77
and J71 connect the input signal pair to J86 and J87 (outputs to the oscilloscope) directly. So, this jumper
configuration makes this section of the board a straight through connection just like the Differential
Return Loss section of the board, but with multiple jumpers in the signal path.
Note: The Mode 1 and Mode 4 tests as defined in 802.3-2005 require the disturbing sine wave. Running the test without the
disturbing sine wave can be informative but it is not a required test.
1000BaseT jitter tests – with and without TX_TCLK
IEEE 802.3-2005 edition states at the end of section 40.6.1.1.3 (Test Fixtures): “Additionally, to allow for
measurement of transmitted jitter in master and slave modes, the PHY shall provide access to the 125MHz
symbol clock, TX_TCLK, that times the transmitted symbols
The PHY shall provide a means to enable this
clock output if it is not normally enabled.” (Emphasis is ours.) This statement is reflected by two items in the
protocol implementation conformance statement (PICS) proforma for Clause 40, in 40.12.7 (PMA Electrical
Specifications), PME42 and PME43. The same text appeared in previous versions of the 802.3 specification back
to IEEE 802.3-2000.
Nonetheless it has become clear that most devices do not provide access to TX_TCLK in production models.
If your DUT does provide access to TX_TCLK please use the “Mode 2 Master Jitter” and “Mode 3 Slave Jitter”
1000BaseT tests. These follow the 802.3 standard.
If your DUT does not provide access to TX_TCLK, then use the “Mode 2 w/o clk Master Jitter” and “Mode 3 w/o
clk Slave Jitter” selections. They are discussed as follows.
The “w/o clk” jitter tests are based on “Appendix 40. B – Transmitter Timing Jitter, No TX_TCLK access”, version
1.1 dated March 25, 2002, which is part of the Gigabit Ethernet Consortium Clause 40 PMA Test Suite, version
2.4. The Gigabit Ethernet Consortium is based at the University of New Hampshire Interoperability Lab. This
document can be found at:
HU
ftp://ftp.iol.unh.edu/pub/ethernet/test_suites/CL40_PMA/PMA_Test_Suite_v2.4.pdf
U
This procedure was not proposed for inclusion in 802.3-2005, almost certainly because, as it says, “this procedure
deviates from the specifications outlined in Clause 40.6.1.2.5, it is not intended to serve as a legitimate substitute
for that clause, but rather as an informal test that may provide some useful insight
” Nonetheless tests based on
this appendix have become the accepted way to measure jitter on devices that do not provide access to
TX_TCLK, as reflected in the GEC’s PMA Test Suite.