Acer Altos G520 - Manual (Page 172)

Appendix F: Diagnostic Code Checkpoints 162
05 OFF G OFF G Initializes the interrupt
controlling hardware
(generally PIC) and
interrupt vector table.
06 OFF G G OFF Do R/W test to CH-2 count
reg. Initialize CH-0 as
system timer. Install the
POSTINT1Ch handler.
Enable IRQ-0 in PIC for
system timer interrupt.
Traps INT1Ch vector to
"POSTINT1ChHandlerBloc
k."
08 G OFF OFF OFF Initializes the CPU. The
BAT test is being done on
KBC. Program the
keyboard controller
command byte is being
done after Auto detection
of KB/MS using AMI KB-5.
CO R R OFF OFF Early CPU Init Start --
Disable Cache - Init Local
APIC
C1 R R OFF G Set up boot strap
processor information
C2 R R G OFF Set up boot strap
processor for POST
C5 R A OFF G Enumerate and set up
application processors
C6 R A G OFF Re-enable cache for boot
strap processor
C7 R A G G Early CPU Init Exit
Check
point
Diagnostic LED Decoder
Description G=Green, R=Red, A+Amber
MSB LSB
BB!H631!.!FO/cppl!!Qbhf!273!!Uvftebz-!Bvhvtu!28-!3115!!5;13!QN