Diodes AP65550 - Manual (Page 12)

AP65550
Document number: DS36336 Rev. 2 - 2
12 of 14
www.diodes.com
April 2014
© Diodes Incorporated
AP65550
Application Information
(cont.)
Output Capacitor (cont.)
Maximum capacitance required can be calculated from the following equation:
ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated from the equation below:
ESR * ΔI Vout
inductor capacitor

An output capacitor with ample capacitance and low ESR is the best option. For most applications, a 22µF to 68µF ceramic capacitor will be
sufficient.
2
out
2
out
2 inductor
out
o
V ) V V ( Δ
)
2
ΔI
L(I
C
 


Where ΔV is the maximum output voltage overshoot.
Bootstrap Capacitor
To ensure the proper operation, a ceramic capacitor must be connected between the VBST and SW pin. A 0.1µF ceramic capacitor is sufficient.
VREG5 Capacitor
To ensure the proper operation, a ceramic capacitor must be connected between the VREG5 and GND pin. A 1µF ceramic capacitor is sufficient.
PC Board Layout
1. The AP65550 works at 5A load current, heat dissipation is a major concern in layout the PCB. A 2oz Copper in both top and bottom
layer is recommended.
2. Provide sufficient vias in the thermal exposed pad for heat dissipate to the bottom layer.
3. Provide sufficient vias in the Output capacitor GND side to dissipate heat to the bottom layer.
4. Make the bottom layer under the device as GND layer for heat dissipation. The GND layer should be as large as possible to provide
better thermal effect.
5. Make the Vin capacitors as close to the device as possible.
6. Make the VREG5 capacitor as close to the device as possible.
7. The thermal pad of the device should be soldered directly to the PCB exposed copper plane to work as a heatsick. The thermal vias in
the exposed copper plane increase the heat transfer to the bottom layer.
Figure 6. PC Board Layout