Rainbow Electronics MAX3420E - Manual (Page 18)

MAX3420E
pre-shutdown tasks before it requests the MAX3420E to
enter the power-down state by setting PWRDOWN = 1.
Wakeup and USB Resume
The MAX3420E may wake up in three ways while it is in
the power-down state:
(1) The SPI master clears the PWRDOWN bit in the
USBCTL (R15) register (this is also achieved by a
chip reset).
(2) The SPI master signals a USB remote wakeup by
setting the SIGRWU bit in the USBCTL (R15) regis-
ter. When SIGRWU = 1, the MAX3420E restarts the
oscillator and waits for it to stabilize. After the oscil-
lator stabilizes, the MAX3420E drives RESUME sig-
naling (a 10ms K-state) on the bus. The MAX3420E
times this interval to relieve the SPI master of having
to keep accurate time. The MAX3420E also ensures
that the RESUME signal begins only after at least
5ms of the bus idle state. When the MAX3420E fin-
ishes its RESUME signaling, it sets the RWUDNIRQ
(remote-wakeup-done interrupt request) interrupt
flag in the USBIRQ (R13) register. At this time the
SPI master should clear the SIGRWU bit.
(3) The host resumes bus activity. To enable the
MAX3420E to wake up from host signaling, the SPI
master sets the HOSCSTEN (host oscillator start
enable) bit of the USBCTL (R15) register. While in
this mode, if the MAX3420E detects a 1 to 0 transi-
tion on D+, the MAX3420E restarts the oscillator
and waits for it to stabilize.
Device Reset
The MAX3420E has three reset mechanisms:
• Power-On Reset. This is the most inclusive reset
(sets all internal register bits to a known state).
• Chip Reset. The SPI master can assert a chip
reset by setting the bit CHIPRES = 1, which has
the same effect as pulling the
RES pin low. This
reset clears only some register bits and leaves
others alone.
• USB Bus Reset. A USB bus reset is the least
inclusive (clears the smallest number of bits).
Power-On Reset
At power-on, all register bits except three are cleared.
The following three bits are set to 1 to indicate that the
IN FIFOs are available for loading by the SPI master
(BAV = buffer available):
• IN3BAVIRQ
• IN2BAVIRQ
• IN0BAVIRQ
Chip Reset
Pulling the RES pin low or setting CHIPRES = 1 clears
most of the bits that control USB operation, but keeps
the SPI and pin-control bits unchanged so the interface
between the SPI master and the MAX3420E is not dis-
turbed. Specifically:
• CHIPRES is unchanged. If the SPI master asserted
this reset by setting CHIPRES = 1, it removes the
reset by writing CHIPRES = 0.
• CONNECT is unchanged, keeping the device
connected if CONNECT = 1.
• The general-purpose outputs GPOUT3–GPOUT0
are unchanged, preventing output glitches.
• The GPX output selector (GPXB, GPXA) is
unchanged.
• The bits that control the SPI interface are
unchanged: FDUPSPI, INTLEVEL, and POSINT.
• The bits that control power-down and wakeup
behavior are unchanged: HOSCSTEN, PWRDOWN,
and SIGRWU.
All other bits except the three noted in the Power-On
Reset section are cleared.
Note: The IRQ and IE bits are cleared using this reset.
This means that firmware routines that enable interrupts
should be called after a reset of this type.
USB Bus Reset
When the MAX3420E detects 21.33µs of SE0, it asserts
the URESIRQ bit and clears certain bits. This reset is
the least inclusive of the three resets. It maintains the
bit states listed in the Power-On Reset and Chip Reset
sections, plus it leaves the following bits in their previ-
ous states:
• Registers R0-R4 are unchanged. The actual data
in the FIFOs is never cleared.
• The IE bit is unchanged.
• URESIE, URESIRQ, URESDNIE, and URESDNIRQ
are unchanged, allowing the SPI master to check
the state of USB bus resets.
As with the chip reset, most of the interrupt request and
interrupt enable bits are cleared, meaning that the
device firmware must reenable individual interrupts after
a bus reset. The exceptions are the interrupts associat-
ed with the actual bus reset, allowing the SPI master to
detect the beginning and end of the host signaling USB
bus reset.
USB Peripheral Controller
with SPI Interface
18 ______________________________________________________________________________________