Rainbow Electronics MAX3420E - Manual (Page 14)

MAX3420E
(R17) register to make INT active high, and clear the
POSINT bit to make INT active low.
GPIN3–GPIN0, GPOUT3–GPOUT0 and GPX
The MAX3420E has four general-purpose inputs
(GPIN3–GPIN0), four general-purpose outputs
(GPOUT3–GPOUT0), and a multiplexed output pin
(GPX). GPIN3 through GPIN0 all have weak internal
pullup resistors to V
L . These inputs can be read by
sampling bits 7 through 4 of the IOPINS (R20) register.
Writing to GPIN3 through GPIN0 has no effect.
GPOUT3 through GPOUT0 are the general-purpose
outputs. Update these outputs by writing to bits 3
through 0 of the IOPINS (R20) register. GPOUT3–
GPOUT0 logic levels are referenced to the voltage on
V
L . As shown in Figure 11, reading the state of a
GPOUT3–GPOUT0 bit returns the state of the internal
register bit, not the actual pin state. This is useful for
doing read-modify-write operations to an output pin
(such as blinking an LED), since the load on the output
pin does not affect the register logic state.
GPX is a push-pull output with a 4-way multiplexer that
selects its output signal. The logic level on GPX is refer-
enced to V
L . The SPI master writes to the GPXB and
GPXA bits of PINCTL (R17) register to select one of four
internal signals as depicted in Table 3.
• OPERATE: This signal goes high when the
MAX3420E is able to operate after a power-up or
RES reset. OPERATE is the default GPX output.
• VBUS_DET: VBUS_DET is the VBCOMP comparator
output. This allows the user to directly monitor the
V
BUS
status.
• BUSACT: USB BUS activity signal (active-high).
This signal is active whenever there is traffic on
the USB bus. The BUSACT signal is set whenever
a SYNC field is detected. BUSACT goes low during
bus reset or after 32-bit times of J-state.
• SOF: A square wave with a positive edge that
indicates the USB start of frame (Figure 12).
MOSI (Master-Out, Slave-In) and
MISO (Master-In, Slave-Out)
The SPI data pins MOSI and MISO operate differently
depending on the setting of a register bit called FDUPSPI
(full-duplex SPI). Figure 13 shows the two configurations
according to the FDUPSPI bit setting.
USB Peripheral Controller
with SPI Interface
14 ______________________________________________________________________________________ 14 ______________________________________________________________________________________
REGISTER BIT
GPOUT
WRITE
GPOUT
READ
GPOUT
PIN
Figure 11. Behavior of Read and Write Operations on
GPOUT3–GPOUT0
Table 3. GPX Output State
GPXB GPXA GPX PIN OUTPUT
0 0 OPERATE (Default State)
0 1 VBUS_DET
1 0 BUSACT
1 1 SOF
FULL-SPEED
TIME FRAME
1ms
FULL-SPEED
TIME FRAME
1ms
SOF
USB
PACKETS
GPX
SOF SOF
~50%
Figure 12. GPX Output in SOF Mode
FDUPSPI = 1
FDUPSPI = 0
(DEFAULT)
MAX3420E
MAX3420E
MOSI
MISO
MOSI
MISO
Figure 13. MAX3420E SPI Data Pins for Full-Duplex (Top) and
Half-Duplex (Bottom) Operation