Pin description (continued) – Rainbow Electronics MAX2063 User Manual
Page 14
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
14
Pin Description (continued)
PIN
NAME
FUNCTION
8
V
CC_RG
Regulator Supply Input. Connect to a 3.3V or 5V external power supply. V
CC_RG
powers all
circuits except for the driver amplifiers. Bypass with a 10nF capacitor as close as possible to
the pin.
9
STA_B_2
Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 2
State A
State B
Digital Attenuator 2
Logic = 0
Logic = 0
Preprogrammed State 1
Logic = 1
Logic = 0
Preprogrammed State 2
Logic = 0
Logic = 1
Preprogrammed State 3
Logic = 1
Logic = 1
Preprogrammed State 4
10
STA_A_2
11
D_ATT_IN_2
5-Bit Digital Attenuator Input (50I), Path 2. Requires a DC-blocking capacitor.
14
D0_2
1dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
15
D1_2
2dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
16
D2_2
4dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
17
D3_2
8dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
18
D_ATT_OUT_2
5-Bit Digital Attenuator Output (50I), Path 2. Requires a DC-blocking capacitor. Connect to
AMP_IN_2 through a 1000pF capacitor.
19
D4_2
16dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable.
21
DA_SP
Digital Attenuator Serial/Parallel Control Select. Set DA_SP to 1 to select serial control. Set
DA_SP to 0 to select parallel control.
24
V
CC_AMP_2
Driver Amplifier Supply Voltage Input, Path 2. Bypass with a 10nF capacitor as close as
possible to the pin.
26
AMP_IN_2
Driver Amplifier Input (50I), Path 2. Connect to D_ATT_OUT_2 through a 1000pF capacitor.
27
PD_2
Power-Down, Path 2. See Table 2 for operation details.
29
AMP_OUT_2
Driver Amplifier Output (50I), Path 2. Connect a pullup inductor from AMP_OUT_2 to V
CC_
.
30
REG_OUT
Regulator Output. Bypass with a 1FF capacitor.
31
AMPSET
Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V on pins V
CC_AMP1
and
V
CC_AMP2
. Set to logic 0 for 5V.
32
AMP_OUT_1
Driver Amplifier Output (50I), Path 1. Connect a pullup inductor from AMP_OUT_1 to V
CC_
.
34
PD_1
Power-Down, Path 1. See Table 2 for operation details.
35
AMP_IN_1
Driver Amplifier Input (50I), Path 1. Connect to D_ATT_OUT_1 through a 1000pF capacitor.
37
V
CC_AMP_1
Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as
possible to the pin.
42
D4_1
16dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable, path 1.
43
D_ATT_OUT_1
5-Bit Digital Attenuator Output (50I), Path 1. Requires a DC-blocking capacitor. Connect to
AMP_IN_1 through a 1000pF capacitor.
44
D3_1
8dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
45
D2_1
4dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
46
D1_1
2dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
47
D0_1
1dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
—
EP
Exposed Pad. Internally connected to GND. Connect to a large PCB ground plane for proper
RF performance and enhanced thermal dissipation.