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U3745bm – Rainbow Electronics U3745BM User Manual

Page 20

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20

U3745BM

4663A–RKE–06/03

Table 9. Effect of the Configuration Word Lim_min

Table 10. Effect of the Configuration Word Lim_max

Conservation of the Register
Information

The U3745BM has an integrated power-on reset and brown-out detection circuitry to
provide a mechanism to preserve the RAM register information.

According to Figure 18, a power-on reset (POR) is generated if the supply voltage V

S

drops below the threshold voltage V

ThReset

. The default parameters are programmed into

the configuration registers in that condition. Once V

S

exceeds V

ThReset

, the POR is can-

celed after the minimum reset period t

Rst

. A POR is also generated when the supply

voltage of the receiver is turned on.

To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a
reset. The RM is represented by the fixed frequency f

RM

at a 50% duty cycle. RM can be

canceled via an ‘L’ pulse t1 at pin DATA. The RM implies the following characteristics:

f

RM

is lower than the lowest feasible frequency of a data signal. By this means, RM

cannot be misinterpreted by the connected microcontroller.

Lim_min

Lower Limit Value for Bit Check

Lim_min < 10 is not applicable

(T

Lim_min

= Lim_min

´

XLim

´

T

Clk

)

0

0

1

0

1

0

10

0

0

1

0

1

1

11

0

0

1

1

0

0

12

0

0

1

1

0

1

13

0

0

1

1

1

0

14 (Default)

(USA: T

Lim_min

= 228 µs, Europe: T

Lim_min

= 232 µs)

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1

1

1

1

0

1

61

1

1

1

1

1

0

62

1

1

1

1

1

1

63

Lim_max

Upper Limit Value for Bit Check

Lim_max < 12 is not applicable

(T

Lim_max

= (Lim_max - 1)

´

XLim

´

T

Clk

)

0

0

1

1

0

0

12

0

0

1

1

0

1

13

0

0

1

1

1

0

14

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

0

1

1

0

0

0

24 (Default)

(USA: T

Lim_max

= 375 µs, Europe: T

Lim_max

= 381 µs)

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1

1

1

1

0

1

61

1

1

1

1

1

0

62

1

1

1

1

1

1

63