Xilinx V2.1 - Manual (Page 25)

Basic Elements 25
Xilinx Blocks
The wrapper file is named to match the top level VHDL file generated for your
project. For example, if your top level file is named
design_project , the
wrapper is called design_project_testbench.vhd . The top level of the
project is taken to be the Simulink sheet from which you invoked the System
Generator token.
In addition to the testbench VHDL file, test vectors ( .dat files) are also generated.
These vectors represent the inputs and expected outputs seen in Simulink
simulation. The testbench (which uses these test vectors) can be run in a
behavioral simulator such as ModelSim from Model Technology. It will report any
discrepancies between the Simulink and VHDL simulations.
•
Global Clock Enable and Global Clear
A global clock enable or clear clock signal can be added to the design by selecting
these options. This may result in a large fanout signal thus degrading system
performance. Use this option only if absolutely necessary.
•
Override with Doubles
The System Generator token allows you to override fixed point values with
double precision values for your Simulink simulation. This is particularly useful
during design and debugging. The
Override with Doubles directive from a
System Generator token is applied to all Xilinx blocks on the same sheet and
recursively through all subsystems on the sheet. Additional System Generator
tokens can be inserted into the subsystems to selectively mask this effect. For an
explanation of the
Override with Doubles behavior, see the Common
Parameters section of the previous chapter.
•
Generate Cores
The Generate Cores pulldown menu on the System Generator token gives three
ways to determine for which blocks the Xilinx LogiCOREs should be generated. They
are:
♦
According to Block Masks : Each block that uses a Xilinx LogiCORE has
a Generate Core checkbox on its parameters dialog box. When
According to Block Masks is selected on the System Generator dialog,
a core is generated for each block whose Generate Core box is checked.
♦
Everywhere Available : When Everywhere Available is selected,
cores are generated without regard to the settings of Generate Core check-
boxes on individual blocks.
♦
Not Needed - Already Generated : When Not Needed - Already
Generated is selected, no cores are generated. This is useful in the early
stages of design development because it saves the time that would otherwise
be used in unnecessary calls to the Xilinx CORE Generator. When, in the later
stages, you plan to run the design through the Xilinx Implementation tools,
you must remember to regenerate your design with
According to Block
Masks or Everywhere Available selected so that your cores are up to
date.
•
Generate button
Finally, clicking the Generate button invokes the code generation software, and
your Simulink design is converted to VHDL and Xilinx LogiCOREs. Note that the
Cancel button is active during code generation. If you want to cancel the code
generation phase while it is running, you may do so by selecting Cancel during
code generation.