Xilinx SP605 - Manual (Page 35)

SP605 Hardware User Guide www.xilinx.com 35
UG526 (v1.8) September 24, 2012
Detailed Description
References
See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information.
[Ref 17]
Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide. [Ref 7]
U22 PHY_RXD7 120 RXD7
AB7 PHY_TXC_GTPCLK 14 GTXCLK
L20 PHY_TXCLK 10 TXCLK
U8 PHY_TXER 13 TXER
T8 PHY_TXCTL_TXEN 16 TXEN
U10 PHY_TXD0 18 TXD0
T10 PHY_TXD1 19 TXD1
AB8 PHY_TXD2 20 TXD2
AA8 PHY_TXD3 24 TXD3
AB9 PHY_TXD4 25 TXD4
Y9 PHY_TXD5 26 TXD5
Y12 PHY_TXD6 28 TXD6
W12 PHY_TXD7 29 TXD7
Table 1-15: Ethernet PHY Connections (Cont’d)
U1 FPGA Pin Schematic Net Name
U46 M88E111
Pin Number Pin Name