Revision history – Xilinx SP605 User Manual
Page 2

SP605 Hardware User Guide
UG526 (v1.8) September 24, 2012
© Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included
herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
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Revision History
The following table shows the revision history for this document.
Date
Version
Revision
10/07/09
1.0
Initial Xilinx release.
11/09/09
1.1
• Updated
and
.
• Changed speed grade from -2 to -3.
• Miscellaneous typographical edits.
02/01/10
1.1.1
Minor typographical edits to
and
.
05/18/10
1.2
Updated
. Added Note 6 to
. Updated board connections for
SFP_TX_DISABLE in
. Added note about FMC LPC J63 connector in
. Updated U1 FPGA Pin column for FMC_LA00_CC_P/N in
. Updated description of PMBus Pod and TI Fusion Digital Power Software
. Updated
.
06/16/10
1.3
Updated
2. 128 MB DDR3 Component Memory
. Added note 1 to
.
09/24/10
1.4
Updated description of Fusion Digital Power Software in
02/16/11
1.5
Revised oscillator manufacturer information from Epson to SiTime in
oscillator manufacturer information from Epson to SiTime on page
. Deleted note
on page 44 referring to J55: “Note: This header is not installed on the SP605 as built.”
Revised values for R50 and R216 in
. Revised oscillator manufacturer
information from Epson to SiTime on page
07/18/11
1.6
Corrected “jitter” to “stability” in section
Oscillator (Differential), page 26
. Revised the
feature and notes descriptions for reference numbers
.
Revised FPGA pin numbers for
,
, and table notes in
.
06/19/12
1.7
Removed reference to FPGA speed grade in
2. 128 MB DDR3 Component Memory,
. Added
IIC External Access Header, page 39
. Updated SFP Module connector
reference designator in