Texas Instruments 3138 155 232931 - Manual (Page 33)

CC2420
SWRS041B Page 33 of 89
14.2 Receive mode
In receive mode, the SFD pin goes active
after the start of frame delimiter (SFD)
field has been completely received. If
address recognition is disabled or is
successful, the SFD pin goes inactive
again only after the last byte of the MPDU
has been received. If the received frame
fails address recognition, the SFD pin goes
inactive immediately. This is illustrated in
Figure 13.
The FIFO pin is active when there are one
or more data bytes in the RXFIFO. The
first byte to be stored in the RXFIFO is the
length field of the received frame, i.e. the
FIFO
pin goes active when the length field
is written to the RXFIFO. The FIFO pin
then remains active until the RXFIFO is
empty.
If a previously received frame is
completely or partially inside the RXFIFO,
the FIFO pin will remain active until the
RXFIFO is empty.
The FIFOP pin is active when the number
of unread bytes in the RXFIFO exceeds
the threshold programmed into
IOCFG0.FIFOP_THR
. When address
recognition is enabled the FIFOP pin will
remain inactive until the incoming frame
passes address recognition, even if the
number of bytes in the RXFIFO exceeds
the programmed threshold.
The FIFOP pin will also go active when
the last byte of a new packet is received,
even if the threshold is not exceeded. If
so, the FIFOP pin will go inactive once
one byte has been read out of the
RXFIFO.
When address recognition is enabled,
data should not be read out of the RXFIFO
before the address is completely received,
since the frame may be automatically
flushed by CC2420 if it fails address
recognition. This may be handled by using
the FIFOP pin, since this pin does not go
active until the frame passes address
recognition.
Figure 14 shows an example of pin activity
when reading a packet from the RXFIFO.
In this example, the packet size is 8 bytes,
IOCFG0.FIFOP_THR
= 3 and
MODEMCTRL0.AUTOCRC
is set. The length
will be 8 bytes, RSSI will contain the
average RSSI level during reception of the
packet and FCS/corr contains information
of FCS check result and the correlation
levels.
14.3 RXFIFO overflow
The RXFIFO can only contain a maximum
of 128 bytes at a given time. This may be
divided between multiple frames, as long
as the total number of bytes is 128 or less.
If an overflow occurs in the RXFIFO, this
is signalled to the microcontroller by
making the FIFO pin go inactive while the
FIFOP
pin is active. Data already in the
RXFIFO will not be affected by the
overflow, i.e. frames already received may
be read out.
A SFLUSHRX command strobe is required
after an RXFIFO overflow to enable
reception of new data. Note that the
SFLUSHRX command strobe should be
issued twice to ensure that the SFD pin
goes back to its inactive state.
For security enabled frames, the MAC
layer must read the source address of the
received frame before it can decide which
key to use to decrypt or authenticate. This
data must therefore not be overwritten
even if it has been read out of the RXFIFO
by the microcontroller. If the
SECCTRL0.RXFIFO_PROTECTION
control
bit is set, CC2420 also protects the frame
header of security enabled frames until
decryption has been performed. If no MAC
security is used or if it is implemented
outside the
CC2420 , this bit may be cleared
to achieve optimal use of the RXFIFO.