Texas Instruments TMS320DM646X DMSOC - Manual (Page 47)

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Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields
are equal to EMIF clock cycles minus 1 cycle, the A1CR should be configured as in
Table 30 . In this
example, although the EM_WAIT signal is connected to the R/B signal of the NAND Flash the Extended
Wait mode of the EMIF is not used, therefore the asynchronous wait cycle configuration register (AWCCR)
does not need to be programmed.
Table 30. Configuring A1CR for HY27UA081G1M Example
Parameter Setting
SS Select Strobe mode.
• SS = 0. Places EMIF in Normal Mode.
EW Extended Wait mode enable.
• EW = 0. Disabled Extended wait mode.
W_SETUP/R_SETUP Read/Write setup widths.
• W_SETUP = 0
• R_SETUP = 2
W_STROBE/R_STROBE Read/Write strobe widths.
• W_STROBE = 6
• R_STROBE = 7
W_HOLD/R_HOLD Read/Write hold widths.
• W_HOLD = 1
• R_HOLD = 0
TA Minimum turnaround time.
• TA = 2
ASIZE Asynchronous device bus width.
• ASIZE = 0, select an 8-bit data bus width.
Since this is a NAND Flash example, the EMIF must be configured for NAND Flash mode. This is
accomplished by configuring the NAND Flash control register (NANDFCR) as in
Table 31 . In NANDFCR,
chip select space 2 must be configured with NAND Flash mode enabled.
Table 31. Configuring NANDFCR for HY27UA081G1M Example
Parameter Setting
CS5ECC NAND Flash ECC start for chip select 5.
• CS5ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
CS4ECC NAND Flash ECC start for chip select 4.
• CS4ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
CS3ECC NAND Flash ECC start for chip select 3.
• CS3ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
CS2ECC NAND Flash ECC start for chip select 2.
• CS2ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
CS5NAND NAND Flash mode for chip select 5.
• CS5NAND = 0. NAND Flash mode is disabled.
CS4NAND NAND Flash mode for chip select 4.
• CS4NAND = 0. NAND Flash mode is disabled.
CS3NAND NAND Flash mode for chip select 3.
• CS3NAND = 0. NAND Flash mode is disabled.
CS2NAND NAND Flash mode for chip select 2.
• CS5NAND = 1. NAND Flash mode is enabled.
47 SPRUEQ7C – February 2010 Asynchronous External Memory Interface (EMIF)
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