Renesas CPU Board M3A-HS19 - Manual (Page 31)

Features and Specifications
2.6 LAN Port Interface
Rev.1.01 Oct 28, .2008 2-15
REJ10J1351-0101
2
2.6 LAN Port Interface
An IEEE 802.3 compliant (MAC layer) Ethernet controller and an IEEE802.3/802.3u compliant (10/100 Mbps Ethernet
PHY) physical layer transceiver are embedded in the SH7619 MCU.
Figure 2.6.1 shows the block diagram of LAN port interface.
SH7619 (U1)
3.3 V
LED1
Yellow
LED2
Yellow
LED3
Yellow
LED4
Yellow
SPEED100#
LINK#
CRS#
DUPLEX#
TxP
TxM
RxP
RxM
EXRES1
TSTBUSA
12.4 K(1%)
3 VAGND
3.3 VA
RJ-45 (J5)
TX +
TX −
RX +
RX −
TCT
RCT
3
1
2
4
5
6
7
8
PHY ETC
(MII)
CK_PHY
25.000 MHz-OSC
MII-compliant signal
Figure 2.6.1 LAN Port Interface