Renesas 32185 - Manual (Page 14)

32185/32186/32192/32195/32196 Group
Starter Kit User’s Manual M3A-2154G52B
REJ10B0223-0150/Rev.1.50 Mar 2008 Page 6 of 80
3.4 About M3T-PD32RM
The following describes precautions to be observed when using M3T-PD32RM.
3.4.1 Operating Manuals
To use M3T-PD32RM of M3A-2154G52B, see the manuals shown below.
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M3T-PD32RM release notes
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PD32RM Help
3.4.2 About Break Operation
M3T-PD32RM uses the M32R core’s internal debug circuit (SDI) to realize break functions. For
this reason, the break functions of M3T-PD32RM behave differently from those in conventional
emulators.
Furthermore, because M3T-PD32RM does not have SDI trace pins as corresponding hardware
resources, the trace pin corresponding break functions available with M3T-PD32R-compatible
emulators are not supported.
The following explains the four types of breaks that can be executed with M3T-PD32RM.
(1) Software break
Up to 64 software breakpoints can be set and executed in RAM areas accessible by the target
MCU. No software breakpoints can be set and executed in ROM areas such as the internal flash
memory.
(2) Pre-execution PC break
The M32R core’s internal debug circuit (SDI) allows setting breakpoints, at which to break the
program immediately before executing an instruction (at the address indicated by the program
counter).
For the M3A-2154G52B (32185/32186/32192/32195/32196 Group MCU), four such breakpoints
can be set.
(3) Post-execution PC break
The M32R core’s internal debug circuit (SDI) allows setting one breakpoint, at which to break the
program immediately after executing an instruction (at the address indicated by the program
counter).
(4) Chip break
The M32R core’s internal debug circuit (SDI) allows setting breakpoints, at which to break the
program when accessing memory for read/write.
For M3A-2154G52B (32185/32186/32192/32195/32196 Group MCU), two such breakpoints (level
2) can be set.
* The differences between levels 1 and 2 are outlined below.
Level 1: Whether data which is maskable matches or not can be detected.
Level 2: Data is maskable and an address range can be specified for the target data.