NEC PD78058FY(A) - Manual (Page 313)

313
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78058F SUBSERIES)
Notes 1. Bit 6 (COI) is a read-only bit.
2. Can be used as a port.
3. To use the wake-up function (WUP = 1), clear the bit 5 (SIC) of the interrupt timing specify
register (SINT) to 0.
4. When CSIE0 = 0, COI becomes 0.
5. In the SBI mode, the operation of serial interface channel 0 should be stopped after WUP is
cleared to “0”. If WUP is not cleared to “0”, P25 is fixed to high-level, and it may become
impossible to use it as a normal port.
Remark
×
: don’t care
PMXX : Port Mode Register
PXX : Port Output Latch
SBI mode
6 5 4 3 2 1 0 7
Symbol
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input Clock to SCK0 pin from off-chip
8-bit timer register 2 (TM2) output
0
R/W
1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
1
CSIM00
×
0
1
FF60H 00H R/W Note 1
Address After Reset R/W
R/W CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operation
Mode
Start Bit
SI0/SB0/P25
Pin Function
SO0/SB1/P26
Pin Function
SCK0/P27
Pin Function
Ч
1 0
Ч
0
Ч
0
0
Ч
0
Ч
0
0
1
1
Note 2 Note 2
Note 2 Note 2
MSB
P25 (CMOS
input/output)
SB0 (N-ch
open-drain
input/output)
SB1 (N-ch
open-drain
input/output)
P26 (CMOS
input/output)
WUP
0
1
Wake-up Function Control Note 3
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after bus release
(when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode
R/W
1 1
3-wired serial I/O mode (16.4.2, 3-wire serial I/O mode operation.)
2-wired serial I/O mode (see section 16.4.4, 2-wire serial I/O mode operation.)
SCK0 (CMOS
input/output)
COI
0
Slave Address Comparison Result Flag Note 4
Slave address register (SVA) not equal to serial I/O shift register (SIO0) 0 data
Slave address register (SVA) equal to serial I/O shift register (SIO0) 0 data
R
1
CSIE0
0
Serial Interface Channel 0 Operation Control Note 5
Operation stopped
Operation enabled
R/W
1