NEC PD78058FY(A) - Manual (Page 23)

23
LIST OF FIGURES (1/8)
Figure No. Title Page
3-1 List of Pin Input/Output Circuit .......................................................................................................... 75
4-1 List of Pin Input/Output Circuit .......................................................................................................... 93
5-1 Memory Map (
µ
PD78056F, 78056FY) .............................................................................................. 95
5-2 Memory Map (
µ
PD78058F, 78058FY) .............................................................................................. 96
5-3 Memory Map (
µ
PD78P058F,
µ
PD78P058FY) .................................................................................. 97
5-4 Data Memory Addressing (
µ
PD78056F, 78056FY) ........................................................................... 100
5-5 Data Memory Addressing (
µ
PD78058F, 78058FY) ........................................................................... 101
5-6 Data Memory Addressing (
µ
PD78P058F, 78P058FY) ...................................................................... 102
5-7 Program Counter Format .................................................................................................................. 103
5-8 Program Status Word Format ........................................................................................................... 103
5-9 Stack Pointer Format ........................................................................................................................ 105
5-10 Data to Be Saved to Stack Memory .................................................................................................. 105
5-11 Data to Be Reset from Stack Memory .............................................................................................. 105
5-12 General Register Configuration ........................................................................................................ 107
6-1 Port Types ......................................................................................................................................... 125
6-2 P00 and P07 Block Diagram ............................................................................................................. 131
6-3 P01 to P06 Block Diagram ................................................................................................................ 131
6-4 P10 to P17 Block Diagram ................................................................................................................ 132
6-5 P20, P21, P23 to P26 Block Diagram ............................................................................................... 133
6-6 P22 and P27 Block Diagram ............................................................................................................. 134
6-7 P20, P21, P23 to P26 Block Diagram ............................................................................................... 135
6-8 P22 and P27 Block Diagram ............................................................................................................. 136
6-9 P30 to P37 Block Diagram ................................................................................................................ 137
6-10 P40 to P47 Block Diagram ................................................................................................................ 138
6-11 Block Diagram of Falling Edge Detection Circuit .............................................................................. 138
6-12 P50 to P57 Block Diagram ................................................................................................................ 139
6-13 P60 to P63 Block Diagram ................................................................................................................ 141
6-14 P64 to P67 Block Diagram ................................................................................................................ 141
6-15 P70 Block Diagram ........................................................................................................................... 142
6-16 P71 and P72 Block Diagram ............................................................................................................. 143
6-17 P120 to P127 Block Diagram ............................................................................................................ 144
6-18 P130 and P131 Block Diagram ......................................................................................................... 145
6-19 Port Mode Register Format .............................................................................................................. 148
6-20 Pull-Up Resistor Option Register Format ......................................................................................... 149
6-21 Memory Expansion Mode Register Format ...................................................................................... 150
6-22 Key Return Mode Register Format ................................................................................................... 151
7-1 Block Diagram of Clock Generator ................................................................................................... 156
7-2 Subsystem Clock Feedback Resistor ............................................................................................... 157
7-3 Processor Clock Control Register Format ........................................................................................ 158