Maxim Integrated DS5001FP - Manual (Page 19)

DS5001FP
19 of 26
AC CHARACTERISTICS (continued)
BYTE-WIDE ADDRESS/DATA BUS TIMING
(T
A
= 0°C to +70°C; V
CC
= 5V ±10%)
# PARAMETER SYMBOL MIN MAX UNITS
40
Delay to Byte-Wide Address Valid from
CE1 , CE2 , or CE1N Low During Op Code
Fetch
t
CE1LPA
30 ns
41 Pulse Width of CE 1-4, PE 1-4 or CE1N
t
CEPW
4t
CLK
- 35 ns
42
Byte-Wide Address Hold After CE1 , CE2 , or
CE1N High During Op Code Fetch
t
CE1HPA
2t
CLK
- 20 ns
43
Byte-Wide Data Setup to CE1 , CE2 , or CE1N
High During Op Code Fetch
t
OVCE1H
1t
CLK
+ 40 ns
44
Byte-Wide Data Hold After CE1 , CE2 or
CE1N High During Op Code Fetch
t
CE1HOV
0 ns
45
Byte-Wide Address Hold After CE 1-4,
PE 1-4, or CE1N High During MOVX
t
CEHDA
4t
CLK
- 30 ns
46
Delay from Byte-Wide Address Valid
CE 1-4, PE 1-4, or CE1N Low During MOVX
t
CELDA
4t
CLK
- 35 ns
47
Byte-Wide Data Setup to CE 1-4, PE 1-4, or
CE1N High During MOVX (read)
t
DACEH
1t
CLK
+ 40 ns
48
Byte-Wide Data Hold After CE 1-4,
PE 1-4, or CE1N High During MOVX (read)
t
CEHDV
0 ns
49
Byte-Wide Address Valid to R/ W Active
During MOVX (write)
t
AVRWL
3t
CLK
- 35 ns
50
Delay from R/ W Low to Valid Data Out
During MOVX (write)
t
RWLDV
20 ns
51
Valid Data-Out Hold Time from CE 1-4,
PE 1-4, or CE1N High
t
CEHDV
1t
CLK
- 15 ns
52 Valid Data-Out Hold Time from R/ W High t
RWHDV
0 ns
53 Write Pulse Width (R/ W Low Time) t
RWLPW
6t
CLK
- 20 ns