FUJITSU SPARC ENTERPRISE M5000 - Manual (Page 302)

F-2 SPARC Enterprise M4000/M5000 Servers Service Manual • August 2009
DIMM Dual inline memory module
DRAM Dynamic random access memory
Ecache External cache
ECC Error correction code
FANBP Fan backplane
FMA Fault management architecture
FRU Field-replaceable unit
FMEMA F loating memory address
GBps Gigabyte per second
GHz Gigahertz
GUI Graphical user interface
HDD H ard disk drive
HDDBP H ard disk drive backplane
I2C bus Inter integrated circuit bus
ISA Instruction set architecture
IOBP I/O backplane
IOU I/O unit
LCD L iquid crystal display
LED Light emitting diode
LSB L ogical system board
LSI Large scale integration
MAC Media access control address
MBC M aintenance bus controller
MEMB Memory modules
MBU Motherboard unit
NTP N etwork time protocol
NVRAM Non-volatile random access memory
OPNL O perator panel
OS Operating system
PCIe PCI express
TABLE F-1 (Continued)Acronyms
Abbreviation Full name