Quantum 10K II - Manual (Page 336)

Appendix B. SCSI Bus Signal Timing
Quantum Atlas 10K II Ultra 160/m SCSI Hard Disk Drives B–15
The drive:
8. Determines that it is selected when the SEL signal and its SCSI ID bit are true
and the BSY and I/O signals are false for at least one bus settle delay.
9. Can examine the DATA BUS to determine the SCSI ID of the selecting initiator.
10. Asserts the BSY signal within a selection abort time of its most recent detection
of being selected.
This is required for correct operation of the selection time-out procedure.
The drive does not respond to a selection if bad parity is detected. Also, if more
than two SCSI ID bits are on the DATA BUS, the drive does not respond to
selection.
11. Waits until the SEL signal is false.
12. Asserts the REQ signal to enter an information transfer phase.
Selection Time-Out
Two optional time-out procedures are specified for clearing the SCSI bus if the
initiator waits a minimum of a selection time-out delay and there has been no BSY
signal response from the drive.
1. The initiator asserts the RST signal.
2. The initiator follows these steps:
a. continues asserting the SEL and ATN signals and releases the DATA BUS.
b. If it has not detected the BSY signal to be true after at least a selection
abort time plus two deskew delays, the initiator releases the SEL and ATN
signals, allowing the SCSI bus to go to the BUS FREE phase.
When responding to selection, SCSI devices ensure that the selection was still valid
within a selection abort time of their assertion of the BSY signal. Failure to comply
with the requirement could result in an improper selection.
B.5.4 RESELECTION Phase
RESELECTION is an optional phase that allows a drive to reconnect to an initiator
to continue an operation that was previously started by the initiator but was
suspended by the drive.
The initiator determines that it is reselected when the SEL and I/O signals and its
SCSI ID bit are true, and the BSY signal is false for at least one bus settle delay.
Reselection Sequence
The drive:
1. Upon completing the ARBITRATION phase, asserts both the BSY and SEL
signals.
2. Delays at least one bus clear delay plus one bus settle delay.
3. Asserts the I/O signal.