Avago Technologies PEX 8605 - Manual (Page 6)

PEX8605
© PLX Technology, www.plxtech.com Page 6 of 13 2 May 2013, version 1.7
Signal Name Dual-Row
QFN Pkg.
Pin # TQFP
Package
Pin # Signal
Type Checked Recommendations
STRAP_UPCFG_TIMER_EN# A28 53
I
PU
YES
NO
UNKNOWN
Link Upconfigure Timer Enable
This input maps to the Debug Control register
UPCFG Timer Enable bit. This signal and its
corresponding register bit must NOT be toggled
at runtime.
When STRAP_UPCFG_TIMER_EN# is pulled
high, the Data Rate Identifier symbol in the TS
Ordered-Sets always advertises support for both
the 5 GT/s (Gen 2) data rate and Autonomous
Change.
When STRAP_UPCFG_TIMER_EN# is pulled
low, if this Link training sequence fails during
the Configuration state, the next time the LTSSM
exits the Detect state, TS Ordered-Sets advertise
only the 2.5 GT/s (Gen1) data rate and no
Autonomous Change. The LTSSM then
continues to toggle between Gen1 and Gen2
advertisement every time it exits Detect state.
NOTE: This feature should only be enabled if a
non-compliant device will not link up when
these Data Rate Indentifier bits are set.
(if adding an option resistor to pull this ball low,
a default pull-up resistor should also be used)
2.7 PCI Express Interface
Signal Name Dual-
Row QFN
Pkg.
Pin # TQFP
Package
Pin # Signal
Type Checked Recommendations
PEX_PERn[3:0]
A61, B47,
B10, A6
121, 108,
19, 7
CMLRn
YES
NO
UNKNOWN
Negative Half of PCI Express Receiver
Differential Signal Pairs for lanes 2:0 (3 Pins)
PEX_PERp[3:0] A62, A55,
A11, A5
122, 109,
18, 6
CMLRp
YES
NO
UNKNOWN
Positive Half of PCI Express Receiver
Differential Signal Pairs for lanes 2:0 (3 Pins)
PEX_PETn[3:0] A59, A52,
A14, A8
117, 104,
23, 11
CMLTn
YES
NO
UNKNOWN
Negative Half of PCI Express Transmitter
Differential Signal for lanes 2:0 (3 Pins)
100 nF AC coupling caps required on all PCI
Express transmit pairs.
PEX_PETp[3:0]
A60, A53,
B11, B6
118, 105,
22, 10
CMLTp
YES
NO
UNKNOWN
Positive Half of PCI Express Transmitter
Differential Signal Pairs for lanes 2:0 (3 Pins)
100 nF AC coupling caps required on all PCI
Express transmit pairs.