Avago Technologies PEX 8605 User Manual
Avago Technologies Hardware
PEX8605
© PLX Technology, www.plxtech.com
Page 1 of 13
2 May 2013, version 1.7
1 Introduction
This document is intended for systems design engineers incorporating the PEX8605 PCI Express switch into a
system hardware design. It provides a handy list of basic design checks covering schematic and printed-circuit
board (PCB) layout designs. Including these checks as part of your design review can help insure that
important details are not overlooked when your design is committed to hardware, thereby improving your
chances for a successful bring-up. In preparation for your design review, we also recommend that you check
our website
documentation. This document supersedes and replaces previously dated versions.
2 Schematic Design Checks
This section includes checks on basic elements of the circuit design, including schematic symbol, power
supply, configuration straps, clocks, reset, configuration serial EEPROM, I2C, JTAG, GPIO, and other signals.
All power and signal pins on the device are covered.
2.1 Schematic Symbol
For designers using ORCAD schematic capture tools, an ORCAD symbol library is available on the PLX
website a
For designers not using the PLX-supplied schematic symbol, we highly recommend double-checking your
symbol’s signal pin names and numbers for accuracy before using the symbol in your schematic design.
2.2 Power Supply
2.2.1 Regulated DC Supply Voltages
The PEX8605 requires the following regulated DC voltages:
Core Logic Supply: 1.0 Volts (0.95V – 1.10V) – Powers core logic, SerDes Digital, and PLL
IO Supply: 2.5 or 3.3 Volts (2.3V – 3.6V) - Powers external I/O, SerDes Analog
2.2.2 Power Supply Sequencing Requirements
The Core Logic and IO supplies can be sequenced in any order. No special hardware is required to control the
order in which the power supply rails power up and down. It is recommended that both supplies be powered
up or down together.