Pinout, Fpga, Rsls – Sundance SMT398VP User Manual
Page 25: Clocks, Table 7:rsl reference clocks
6. PINOUT
6.1.
FPGA
6.1.1. RSLs
6.1.1.1.
Clocks
P GCLK4S
E20
BREFCLK
N GCLK5P
D20
LVPECL
Clock
synthesiser
P GCLK2S
Top
BREFCLK2
N GCLK3P
Unconnected Unconnected
P GCLK6P
AT20
BREFCLK
N GCLK7S
AR20
LVPECL
Clock
synthesiser
P GCLK0P
Bottom
BREFCLK2
N GCLK1P
Unconnected Unconnected
Table 7:RSL reference clocks
Document No.
S M T 3 9 8 V P - D 0 0 0 0 5 8 H - g u i d e . d o c
Revision
2 . 4 . 2
Date
0 8 / 0 2 / 0 7
Page 25 of 34
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