Sundance SMT398VP - Manual (Page 22)

For 1 QDR II Bank the termination at the memory is:
• QQ[35:0] : 36 termination resistors
• QD[35:0] : 36 termination resistors
• QSA[19:0] : 20 termination resistors
• QWn, QRn 2 termination resistors
• QK, QKn: 2 termination resistors
• QC, QCn: 2 termination resistors
• CQ, CQn: 2 termination resistors
So a total of 100 termination resistors per bank.
Please refer to the various specifications.
Links to these specifications can be found at: 2.1.2.
4.1.6.2. Termination and transmission lines
Signal At the FPGA Terminations at the
FPGA Termination at
memory
1 Write Data to memory(QD) OBUF_HSTL_II_18 SSTL2_II_DCI HSTL_II_18 Split
termination
2 Read Data from memory(QQ) IBUF_HSTL_I_DCI_18 HSTL_II_18 100 ohm pull-up to
1.3v
3 Data Strobe(CQ, CQn) HSTL_II_18 SSTL2_II_DCI 50 ohm pull-up to
1.3v
4 Clock(QC, QCn, QK, QKn, ) HSTL_II_18 SSTL2_II_DCI 50 ohm pull-up to
1.3v
5 Address(QSA) HSTL_II_18 SSTL2_II_DCI 50 ohm pull-up to
1.3v
6 Control(QWn, QRn) HSTL_II_18 SSTL2_II_DCI 50 ohm pull-up to
1.3v
Table 6: QDR II termination scheme
No more than 1 split termination type allowed per bank
Document No.
S M T 3 9 8 V P - D 0 0 0 0 5 8 H - g u i d e . d o c
Revision
2 . 4 . 2
Date
0 8 / 0 2 / 0 7
Page 22 of 34