Interface definition, Major features, Prime item characteristics – Sundance SMT398VP User Manual
Page 12: Fpga, Cpld, Prom
4.1.2. Interface Definition
For the TIM to carrier board or external world interfacing, see in
you can download from this link)
4.1.3. Major features
• Block1: Xilinx Virtex II Pro XC2VP70, configuration scheme and reset scheme.
• Block2: QDR II SRAM memory.
• Block3: IO connectors for general purpose or dedicated interfaces.
• Block4: Clocking scheme performing from 25 MHz up to 700MHz.
• Block5: Leds for development and in-use monitoring and general purpose use.
4.1.4. Prime Item Characteristics
4.1.4.1.
FPGA
Xilinx Virtex II Pro XC2VP70FF1517 FPGA.
This device is packaged in a 1517-pin BGA package with a -6 or -7 speed grade. It
contains 2 PowerPC 405s and up to 16 Rocket-I/Os.
4.1.4.2.
CPLD
Xilinx Coolrunner II device
This device is packaged in a 100-
pin very Thin QFP package with a -6 speed grade.
It provides the option to configure the FPGA via ComPort 0 or 3 at 20Mbytes/s.
Ideal for quick in systems debugging/prototyping and development of your FPGA
design where the SMT398VP is coupled to at least 1 DSP TIM. It also enables in-
system updates.
The CPLD code is NOT to be modified without Sundance approval.
4.1.4.3.
PROM
Programmed via JTAG.
Loads an FPGA configuration bitstream at power up or reset.
Parallel FPGA configuration interface (up to 33 MHz)
Built-in data decompressor compatible with Xilinx advanced compression
technology.
Document No.
S M T 3 9 8 V P - D 0 0 0 0 5 8 H - g u i d e . d o c
Revision
2 . 4 . 2
Date
0 8 / 0 2 / 0 7
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