Qdr ii sram, Figure 3: fpga connections to bank1 of qdrii, Page 15 of 34 – Sundance SMT398VP User Manual
Page 15
4.1.4.7.
QDR II SRAM
Up to 4 Mbytes of QDR II SRAM
The memory is available as 2 independent banks of QDRII. Each bank is arranged as
follows:
Figure 3: FPGA connections to Bank1 of QDRII
QQ[35:0]
QD[35:0]
NC + QSA[16:0]
QWn/QRn
QK/QKn, QC/QCn (output)
CQ/CQn (input)
4
2
R = 50 Ohms
V
TERM
=
V
REF/2
R = 50 Ohms
36
36
20
20
2
Q/Q
n
C/Cn
K/
Kn
Ct
rl
Ad
dr
D
Q
QDRII
Bank x
36
36
2
V
TERM
=
V
REF/2
XC2VP
4 word burst-QDR II at 200MHz in 2 independent banks of 36-bits wide data busses.
The aggregate throughput for data transfers with the QDR II is 28.8 Gb/s, or 400
Mb/s per pin for a 36-bit write bus and a 36-bit read bus operating in DDR mode at
200 MHz.
Each bank is fully independent with separate address, control and data busses.
bers,
fully compatible can be fitted depending on availability at time of order.
Alternative part numbers are:
Specification and implementation documents are available for design details about
using the QDRII .
Document No.
S M T 3 9 8 V P - D 0 0 0 0 5 8 H - g u i d e . d o c
Revision
2 . 4 . 2
Date
0 8 / 0 2 / 0 7
Page 15 of 34