Figure 4: clocking distribution diagram, Of the fpga as pre, Page 19 of 34 – Sundance SMT398VP User Manual
Page 19
A Specification document D000110-spec.pdf about a design programming
the clock synthesiser is available from Sundance. The implementation
reference design is provided with the board package.
• An external clock input is provided to the Virtex II Pro FPGA via an MMCX
connector. This connector is
NOT
fitted by default or if a mezzanine is
required. YOU MUST ask Sundance if needed for your application.
VIIPRO
D20
E20
5p 4s
+ -
CLK
Synthesis
K20
M20
N20
J20
AH21
AJ21
AH20
AL20
AT20
AR20
4p
5s
- +
7s 6p
BANK 0
BANK 1
BANK 5
BANK 4
ShbA
Hw1
Clk
User
CLK
MMCX
(optinal)
CLK
Synthesis
ShbB
Hw0
Clk
ShbB
Hw1
Clk
3p
1p
DCM
[X0,X1]Y1
IN
FB
CLK0
CLKFX
CLK2X
CLKDIV
DCM
[X2,X3]Y1
IN
FB
CLK0
CLKFX
CLK2X
CLKDIV
DCM
[X2,X3]Y0
IN
FB
CLK0
CLKFX
CLK2X
CLKDIV
DCM
[X0,X1]Y0
IN
FB
CLK0
CLKFX
CLK2X
CLKDIV
25MHz XTAL
2s
0s
AK20
AG20
QDRII
A
QDRII
B
CQ
AM37
CQ
V38
CQn
R36
CQn
AG30
K
N37
Kn
P37
K
AE37
Kn
AD37
C
Cn
C
Cn
AD32
AC32
N31
M32
S C
L
O
C
K
F15
ShbA
Hw0
Clk
TIM Conn CLKIN
BA
NK 6
BA
N
K
7
BA
NK 3
BA
N
K
2
3s
2p
1s
0p
AK20
50Mhz
osc
6s
7p
M21
L21
Figure 4: Clocking distribution diagram
Document No.
S M T 3 9 8 V P - D 0 0 0 0 5 8 H - g u i d e . d o c
Revision
2 . 4 . 2
Date
0 8 / 0 2 / 0 7
Page 19 of 34