Sundance SMT398VP - Manual (Page 13)

4.1.4.4. JTAG Header
The JTAG header is compatible with Xilinx Parallel-IV cable signals.
It supports code download (for the FPGA Power PC), FPGA configuration,
Hardware and Software Debugging tools for the Virtex-II Pro.
This cable connects the parallel port of an engineer's Workstation/PC to the JTAG
chain of the SMT398VP Module.
All the devices from block1 are chained and accessible via this JTAG header.
4.1.4.5. FPGA Configuration schemes
Different schemes are available to provide maximum flexibility in systems where the
SMT398VP is involved:
The FPGA configuration bitstream source can be:
• one of the 2 ComPorts:
The CPLD is connected to 2 ComPort links of the SMT398VP TIM connector. A
switch (
see Table 3 ) is used to select the configuration ComPort that will be used to
receive the bitstream.
The CPLD allows for FPGA configuration in slave SelectMap mode.
• On-board Flash PROM.
The FPGA configuration is operated in Master SelectMap mode. A switch ( see Table
3 ) is used to select PROM as the configuration source.
• Using the on-board JTAG header and Xilinx JTAG programming tools.
The JTAG header is a Parallel-IV Header.
4.1.4.6. FPGA Reset Scheme
The CPLD is connected to a TIM global Reset signal provided to the SMT398VP via
its primary TIM connector pin 30. (See
Figure 5: Top View)
The CPLD provides another signal called FPGAResetn that offers a better Reset
control over the FPGA.
At power up or on reception of a low TIM global Reset pulse , the CPLD drives the
FPGAResetn signal low and keeps it low .
When the ENDKEY has been received , the CPLD drives FPGAResetn high .
Use FPGAResetn for the Global Reset signal of your FPGA designs.
In this manner, you can control your FPGA design Reset activity and you will also
avoid possible conflicts on ComPort 3 if your FPGA design implements it.
Document No.
S M T 3 9 8 V P - D 0 0 0 0 5 8 H - g u i d e . d o c
Revision
2 . 4 . 2
Date
0 8 / 0 2 / 0 7
Page 13 of 34