Sundance SMT398VP - Manual (Page 21)

4.1.6. Physical Characteristics
4.1.6.1. Power budget
Table 5: Power budget.
Device Quantity Voltage(V) Current(mA) Power(W) Source
Static Power on termination
resistor (50 ohms) (See
details) 200 1.8 16.0 5.76 Virtex II PRO (ds083 module 3 table 6)
HSTL II current specification
Samsung QDR II burst 4
(36-bit interface) 2 1.8 550 1.98 Samsung QDRII datasheet
25 Mhz Clock oscillator 1 3.3 10 0.033 Jauch VX3 Quartz crystal oscillators
datasheet
Digital 3.3 155 0.5115 Clock
synthesizer
Analog
1
3.3 20 0.066
ICS 8442 hih frequency synthesizer
LEDs 5 3.3 25 0.4125
DIP Switch 1 2.5 2.1 0.005 Four 4.7 Kohm pullup
XC2V70 FPGA 1 Must be calculated based on design. Xpower
tool from Xilinx should be used
Coolrunner II CPLD (See
details) 1 1.8 17mA 0.031 CPLD power calculator
Details:
Coolrunner II CPLD power requirement based on design:
During FPGA configuration only, the Coolrunner CPLD power consumption is at its
maximum:
• Macrocells used: 40
• Macrocells used as outputs or bidirectional: 26
• Fmax:100MHz
• The average toggle rate of all flip-flops:40%
• Number of product terms:69
Document No.
S M T 3 9 8 V P - D 0 0 0 0 5 8 H - g u i d e . d o c
Revision
2 . 4 . 2
Date
0 8 / 0 2 / 0 7
Page 21 of 34