Sundance SMT351T - Manual (Page 5)

SMT351T User Guide Page 5 of 37 Last Edited: 04/09/2009 11:26:00
Table of Figures
Figure 1: Block Diagram ........................................................................................................9
Figure 2: CPLD state machine.............................................................................................13
Figure 3: FPGA connections to DDR2SDRAM....................................................................15
Figure 4: FPGA clock buffers usage.....................................................................................19
Figure 5: Top View................................................................................................................22
Figure 6: Bottom view ..........................................................................................................23
Figure 7: JTAG connector Pinout ........................................................................................34
Table of Tables
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Table 1: DIP switch SW1 position for special reset feature
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Table 2: DIP switch SW1 position for the selection of the configuration bitstream source
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Table 3: DIP switch SW1 position for the selection of the Flash erase & program
operations.
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Table 4: Coolrunner II resources summary.
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Table 5:Coolrunner II pin resources.
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